1. Field of the Invention
The present invention relates to a packaging conductive structure for a semiconductor substrate. In particular, the invention relates to a packaging conductive structure with a redistribution layer (RDL).
2. Description of the Related Art
Electronic products have been equipped with semiconductor chips to provide control or logic operation functions. With the recent advancement of manufacturing process technologies, semiconductor chips have miniaturized, thereby, gradually reducing the packaging size.
Due to the miniaturization, the conventional wire bonding techniques for connecting semiconductor chips to other devices are no longer applicable. The flip chip bonding technique has replaced the wire bonding technique for connecting the semiconductor chips to other devices using bumps. More specifically, a plurality of bumps electrically connected to the structure inside the chip is disposed on the surface of the semiconductor chip for bonding purposes. In addition, the flip chip bonding technique does not require a large area, as previously required in the conventional wire technique, making it suitable for advanced process.
Furthermore, the conventional package technology further adopts the design of an RDL. Pads are arranged on the exterior of the integrated circuits (ICs). If bumps are directly formed on the pads, the number for the bumps and pitches between bumps may be limited, causing poor bonding and other defects in the bumps. The RDL has an indirect electrical connection with the bumps and the pads. To increase flexibility, the pads are connected to the bumps through a conductive layer, allowing the bumps to rearrange and not be limited to their original positions.
A conventional packaging structure with an RDL is shown in FIG. 1. A semiconductor chip 10 comprises a substrate 11 with a metallic layer 111 disposed thereon. The metallic layer 111, i.e. pad, serves as a contact point between the inner semiconductor structure and the external devices. A dielectric layer 13 disposed on the substrate 11 overlays the periphery of the metallic layer 111. A portion of the metallic layer 111 is exposed from the dielectric layer 111. Then, an RDL 15 with a deposited conductive layer 151 and protection layer 153 is formed. Next, a through-hole is formed in the protection layer 153 where the bump will be formed. An under bump metallization (UBM) 17 is formed in the through-hole. Finally, the bump 19 is formed. Wherein, the UBM 17 is made of multilayer metallic films of titanium, chromium, copper, gold and so on. The UBM 17 provides the electrical connection and improves the adhesion for the bump, thus providing a stable bonding between the bump 19 and the conductive layer 151. The bump 19 may be electrically connected to the metallic layer 111 of the substrate 11 using the above-mentioned structure. In addition, the bump's position can also be adjusted to increase the flexibility of using the semiconductor chip in the flip chip technique.
However, because the deposition of the conductive layer is unidirectional, it is difficult to form a conductive layer with a thick enough side wall in the dielectric layer 13 during the deposition of the conductive layer 151. As a result, the risk of conductive layer breakage is increased. As shown in the dotted-line area of FIG. 1, it is more difficult to deposit a portion of the conductive layer 151 near the side wall of the dielectric layer 13. The conductive layer 151 may break easily if the process is not controlled well, causing the semiconductor chip to fail.
Accordingly, a solution of providing a packaging conductive structure that can ensure the electrical connection in a semiconductor structure with an RDL is highly desired in semiconductor technology.